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| author |   Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-08-31 18:37:46 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-09-26 16:45:41 +0200 |
| commit | 4f6b07a2787b97380dc278ce28bd4438817f7525 (patch) | |
| tree | 345a6fcf000da5b627b81dc993f0f377c7776a4c /arch/arm/boot/dts/tegra30-apalis.dtsi | |
| parent | ARM: tegra: apalis_t30: add local-mac-address property (diff) | |
| download | linux-dev-4f6b07a2787b97380dc278ce28bd4438817f7525.tar.xz linux-dev-4f6b07a2787b97380dc278ce28bd4438817f7525.zip | |
ARM: tegra: apalis_t30: reorder pcie properties
Reorder PCIe properties.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-apalis.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-apalis.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index f13df31b5e25..fc279a073ac5 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -16,13 +16,13 @@ pcie@3000 { avdd-pexa-supply = <&vdd2_reg>; - vdd-pexa-supply = <&vdd2_reg>; avdd-pexb-supply = <&vdd2_reg>; - vdd-pexb-supply = <&vdd2_reg>; avdd-pex-pll-supply = <&vdd2_reg>; avdd-plle-supply = <&ldo6_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; hvdd-pex-supply = <&sys_3v3_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + vdd-pexa-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; pci@1,0 { nvidia,num-lanes = <4>; |