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authorOlof Johansson <olof@lixom.net>2012-11-29 22:39:11 -0800
committerOlof Johansson <olof@lixom.net>2012-11-29 22:39:11 -0800
commit68fb31706d50dd5d337cd7928aeb780358b910a5 (patch)
tree6632d05aae22e99d7f128104b536bfdfc225a696 /arch/arm/boot/dts/zynq-ep107.dts
parentLinux 3.7-rc7 (diff)
parentMerge tag 'omap-for-v3.8/cleanup-timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup (diff)
downloadlinux-dev-68fb31706d50dd5d337cd7928aeb780358b910a5.tar.xz
linux-dev-68fb31706d50dd5d337cd7928aeb780358b910a5.zip
Merge branch 'next/cleanup' into next/pm2
By Tony Lindgren (36) and others via Tony Lindgren (22) and others * next/cleanup: (303 commits) ARM: Kirkwood: Use hw_pci.ops instead of hw_pci.scan ARM: OMAP3: cm-t3517: use GPTIMER for system clock ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER ARM: SAMSUNG: use devm_ functions for ADC driver ARM: EXYNOS: no duplicate mask/unmask in eint0_15 ARM: S3C24XX: SPI clock channel setup is fixed for S3C2443 ARM: EXYNOS: Remove i2c0 resource information and setting of device names ARM: Kirkwood: checkpatch cleanups ARM: Kirkwood: Fix sparse warnings. ARM: Kirkwood: Remove unused includes ARM: kirkwood: cleanup lsxl board includes ARM: integrator: use BUG_ON where possible ARM: integrator: push down SC dependencies ARM: integrator: delete static UART1 mapping ARM: integrator: delete SC mapping on the CP ARM: integrator: remove static CP syscon mapping ARM: integrator: remove static AP syscon mapping ARM: integrator: hook the CP into the SoC bus ARM: integrator: hook the AP into the SoC bus ARM: OMAP2+: Fix compiler warning for 32k timer ...
Diffstat (limited to 'arch/arm/boot/dts/zynq-ep107.dts')
-rw-r--r--arch/arm/boot/dts/zynq-ep107.dts19
1 files changed, 15 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
index 37ca192fb193..574bc044f572 100644
--- a/arch/arm/boot/dts/zynq-ep107.dts
+++ b/arch/arm/boot/dts/zynq-ep107.dts
@@ -36,16 +36,27 @@
ranges;
intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
interrupt-controller;
- compatible = "arm,gic";
- reg = <0xF8F01000 0x1000>;
- #interrupt-cells = <2>;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xF8F02000 0x1000>;
+ arm,data-latency = <2 3 2>;
+ arm,tag-latency = <2 3 2>;
+ cache-unified;
+ cache-level = <2>;
};
uart0: uart@e0000000 {
compatible = "xlnx,xuartps";
reg = <0xE0000000 0x1000>;
- interrupts = <59 0>;
+ interrupts = <0 27 4>;
clock = <50000000>;
};
};