diff options
| author |   Gregory CLEMENT <gregory.clement@free-electrons.com> | 2012-09-26 18:02:49 +0200 |
|---|---|---|
| committer |   Jason Cooper <jason@lakedaemon.net> | 2012-11-27 15:35:34 +0000 |
| commit | 2f96fbb7d851740d0594a6b74142083d51483ab5 (patch) | |
| tree | 55ed7e2ddd09fbd1866f19f901e2b1b65db9bbb5 /arch/arm/boot | |
| parent | arm: mvebu: add L2 cache support (diff) | |
| download | linux-dev-2f96fbb7d851740d0594a6b74142083d51483ab5.tar.xz linux-dev-2f96fbb7d851740d0594a6b74142083d51483ab5.zip | |
arm: mvebu: add Aurora L2 Cache Controller to the DT
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/armada-370.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-xp.dtsi | 7 |
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 7fbac28b01f3..636cf7d4009e 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -20,6 +20,12 @@ / { model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; + L2: l2-cache { + compatible = "marvell,aurora-outer-cache"; + reg = <0xd0008000 0x1000>; + cache-id-part = <0x100>; + wt-override; + }; aliases { gpio0 = &gpio0; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 45a567c2e9ba..367aa3f94912 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -22,6 +22,13 @@ model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; + L2: l2-cache { + compatible = "marvell,aurora-system-cache"; + reg = <0xd0008000 0x1000>; + cache-id-part = <0x100>; + wt-override; + }; + mpic: interrupt-controller@d0020000 { reg = <0xd0020a00 0x1d0>, <0xd0021070 0x58>; |