aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/include/asm/kvm_host.h
diff options
context:
space:
mode:
authorMarc Zyngier <marc.zyngier@arm.com>2014-01-22 09:43:38 +0000
committerMarc Zyngier <marc.zyngier@arm.com>2014-03-03 01:15:23 +0000
commitac30a11e8e92a03dbe236b285c5cbae0bf563141 (patch)
treefe7e8a2493f46af06b0c59c18f71ab60562b3d15 /arch/arm/include/asm/kvm_host.h
parentARM: KVM: fix ordering of 64bit coprocessor accesses (diff)
downloadlinux-dev-ac30a11e8e92a03dbe236b285c5cbae0bf563141.tar.xz
linux-dev-ac30a11e8e92a03dbe236b285c5cbae0bf563141.zip
ARM: KVM: introduce per-vcpu HYP Configuration Register
So far, KVM/ARM used a fixed HCR configuration per guest, except for the VI/VF/VA bits to control the interrupt in absence of VGIC. With the upcoming need to dynamically reconfigure trapping, it becomes necessary to allow the HCR to be changed on a per-vcpu basis. The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR field, initialized at setup time. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/include/asm/kvm_host.h')
-rw-r--r--arch/arm/include/asm/kvm_host.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 098f7dd6d564..09af14999c9b 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -101,6 +101,12 @@ struct kvm_vcpu_arch {
/* The CPU type we expose to the VM */
u32 midr;
+ /* HYP trapping configuration */
+ u32 hcr;
+
+ /* Interrupt related fields */
+ u32 irq_lines; /* IRQ and FIQ levels */
+
/* Exception Information */
struct kvm_vcpu_fault_info fault;
@@ -128,9 +134,6 @@ struct kvm_vcpu_arch {
/* IO related fields */
struct kvm_decode mmio_decode;
- /* Interrupt related fields */
- u32 irq_lines; /* IRQ and FIQ levels */
-
/* Cache some mmu pages needed inside spinlock regions */
struct kvm_mmu_memory_cache mmu_page_cache;