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| author |   Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-05-03 01:11:25 +0800 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2011-07-28 15:07:28 +0000 |
| commit | 1ff5b1b411bf8a8157ae949a1b3ed8666d96c1db (patch) | |
| tree | e323223c27e8070412f47f9ae09e62cbc2edf71d /arch/arm/mach-at91/include/mach/debug-macro.S | |
| parent | at91: factorize at91 interrupts init to soc (diff) | |
| download | linux-dev-1ff5b1b411bf8a8157ae949a1b3ed8666d96c1db.tar.xz linux-dev-1ff5b1b411bf8a8157ae949a1b3ed8666d96c1db.zip | |
at91: remove AT91_DBGU offset from dbgu register macro
to make the soc base specified at runtime instead of compiled time
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/debug-macro.S')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/debug-macro.S | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S index 0f959faf74a9..bc1e0b2e2f4f 100644 --- a/arch/arm/mach-at91/include/mach/debug-macro.S +++ b/arch/arm/mach-at91/include/mach/debug-macro.S @@ -15,23 +15,23 @@ #include <mach/at91_dbgu.h> .macro addruart, rp, rv - ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) - ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) + ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) + ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) .endm .macro senduart,rd,rx - strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register + strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register .endm .macro waituart,rd,rx -1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register - tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit +1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register + tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit beq 1001b .endm .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register - tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete +1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register + tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete beq 1001b .endm |