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| author |   Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-18 00:28:29 +0800 |
|---|---|---|
| committer |   Nicolas Ferre <nicolas.ferre@atmel.com> | 2012-01-20 17:19:35 +0100 |
| commit | 6522ecdcfaae90ad1d2dd868fbdf3a2ddfc5f257 (patch) | |
| tree | 2d09bd02ec649657dfce40c6762a91639776a43e /arch/arm/mach-at91/include | |
| parent | ARM/USB: at91/ohci-at91: rename vbus_pin_inverted to vbus_pin_active_low (diff) | |
| download | linux-dev-6522ecdcfaae90ad1d2dd868fbdf3a2ddfc5f257.tar.xz linux-dev-6522ecdcfaae90ad1d2dd868fbdf3a2ddfc5f257.zip | |
ARM: at91: fix cap9 ddrsdr register
fix AT91_DDRSDRC_MODE it's 3bit
add missing AT91_DDRSDRC_NR_14, AT91_DDRSDRC_DBW (16 and 32 bits support)
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h index 976f4a6c3353..d21932dcd6fa 100644 --- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h @@ -16,7 +16,7 @@ #define AT91CAP9_DDRSDR_H #define AT91_DDRSDRC_MR 0x00 /* Mode Register */ -#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ +#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ #define AT91_DDRSDRC_MODE_NORMAL 0 #define AT91_DDRSDRC_MODE_NOP 1 #define AT91_DDRSDRC_MODE_PRECHARGE 2 @@ -42,6 +42,7 @@ #define AT91_DDRSDRC_NR_11 (0 << 2) #define AT91_DDRSDRC_NR_12 (1 << 2) #define AT91_DDRSDRC_NR_13 (2 << 2) +#define AT91_DDRSDRC_NR_14 (3 << 2) #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ #define AT91_DDRSDRC_CAS_2 (2 << 4) #define AT91_DDRSDRC_CAS_3 (3 << 4) @@ -86,6 +87,9 @@ #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 #define AT91_DDRSDRC_MD_DDR 2 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 +#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ +#define AT91_DDRSDRC_DBW_32BITS (0 << 4) +#define AT91_DDRSDRC_DBW_16BITS (1 << 4) #define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |