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authorKevin Cernekee <cernekee@gmail.com>2014-11-06 22:44:26 -0800
committerJason Cooper <jason@lakedaemon.net>2014-11-09 04:03:13 +0000
commitc76acf4dffa3232711b5364d7a29746df590f3db (patch)
tree1477f55905d95991574d12a46eb05b17ec2af156 /arch/arm/mach-bcm
parentirqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions (diff)
downloadlinux-dev-c76acf4dffa3232711b5364d7a29746df590f3db.tar.xz
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irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers
Most implementations of the bcm7120-l2 controller only have a single 32-bit enable word + 32-bit status word. But some instances have added more enable/status pairs in order to support 64+ IRQs (which are all ORed into one parent IRQ input). Make the following changes to allow the driver to support this: - Extend DT bindings so that multiple words can be specified for the reg property, various masks, etc. - Add loops to the probe/handle functions to deal with each word separately - Allocate 1 generic-chip for every 32 IRQs, so we can still use the clr/set helper functions - Update the documentation This uses one domain per bcm7120-l2 DT node. If the DT node defines multiple enable/status pairs (i.e. >=64 IRQs) then the driver will create a single IRQ domain with 2+ generic chips. Multiple generic chips are required because the generic-chip code can only handle one enable/status register pair per instance. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1415342669-30640-12-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-bcm')
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