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| author |   Andrew Lunn <andrew@lunn.ch> | 2012-05-14 11:28:43 +0200 |
|---|---|---|
| committer | Andrew Lunn <andrew@lunn.ch> | 2012-05-14 18:13:15 +0200 |
| commit | ca2ac5cc9548e954b295de16158a5a7e3b97873b (patch) | |
| tree | 6b04754efe124761ac5a126c3d898923d4fa25c7 /arch/arm/mach-dove | |
| parent | ARM: orion5x: ts78xx debugging changes (diff) | |
| download | linux-dev-ca2ac5cc9548e954b295de16158a5a7e3b97873b.tar.xz linux-dev-ca2ac5cc9548e954b295de16158a5a7e3b97873b.zip | |
Dove: Fix Section mismatch warnings
Add missing __init markups to GPIO and timer functions.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Diffstat (limited to 'arch/arm/mach-dove')
| -rw-r--r-- | arch/arm/mach-dove/common.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-dove/mpp.c | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index bda7aca04ca0..42ab1e7c4ecc 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -181,7 +181,7 @@ static int get_tclk(void) return 166666667; } -static void dove_timer_init(void) +static void __init dove_timer_init(void) { orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_DOVE_BRIDGE, get_tclk()); diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 51e0e411c9cb..7f70afc26f91 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -56,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) /* Dump all the extra MPP registers. The platform code will dump the registers for pins 0-23. */ -static void dove_mpp_dump_regs(void) +static void __init dove_mpp_dump_regs(void) { pr_debug("PMU_CTRL4_CTRL: %08x\n", readl(DOVE_MPP_CTRL4_VIRT_BASE)); @@ -67,7 +67,7 @@ static void dove_mpp_dump_regs(void) pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); } -static void dove_mpp_cfg_nfc(int sel) +static void __init dove_mpp_cfg_nfc(int sel) { u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); @@ -78,7 +78,7 @@ static void dove_mpp_cfg_nfc(int sel) dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); } -static void dove_mpp_cfg_au1(int sel) +static void __init dove_mpp_cfg_au1(int sel) { u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); @@ -118,7 +118,7 @@ static void dove_mpp_cfg_au1(int sel) /* Configure the group registers, enabling GPIO if sel indicates the pin is to be used for GPIO */ -static void dove_mpp_conf_grp(unsigned int *mpp_grp_list) +static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list) { u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); int gpio_mode; |