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| author |   Taras Kondratiuk <taras.kondratiuk@linaro.org> | 2014-01-10 01:27:08 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@arm.linux.org.uk> | 2014-01-12 14:15:27 +0000 |
| commit | b25f3e1c358434bf850220e04f28eebfc45eb634 (patch) | |
| tree | 5b72a6f960fad442b71df141d415eaa8a592c4e8 /arch/arm/mach-footbridge/dc21285-timer.c | |
| parent | ARM: 7939/1: traps: fix opcode endianness when read from user memory (diff) | |
| download | linux-dev-b25f3e1c358434bf850220e04f28eebfc45eb634.tar.xz linux-dev-b25f3e1c358434bf850220e04f28eebfc45eb634.zip | |
ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling
Kexec disables outer cache before jumping to reboot code, but it doesn't
flush it explicitly. Flush is done implicitly inside of l2x0_disable().
But some SoC's override default .disable handler and don't flush cache.
This may lead to a corrupted memory during Kexec reboot on these
platforms.
This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable()
handlers to make it consistent with default l2x0_disable().
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-footbridge/dc21285-timer.c')
0 files changed, 0 insertions, 0 deletions