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authorRob Herring <rob.herring@calxeda.com>2012-10-25 12:13:47 -0500
committerRob Herring <rob.herring@calxeda.com>2012-10-31 13:46:50 -0500
commit7a2848d369b2b9281400e6c9f08e21ec71cd1dcb (patch)
treeabb8983696264faee745f49a8132589134f0e791 /arch/arm/mach-highbank/highbank.c
parentARM: smp_twd: don't warn on no DT node (diff)
downloadlinux-dev-7a2848d369b2b9281400e6c9f08e21ec71cd1dcb.tar.xz
linux-dev-7a2848d369b2b9281400e6c9f08e21ec71cd1dcb.zip
ARM: highbank: abstract out SCU usage
In preparation for A15 support on ECX-2000, the direct calls to SCU registers must be conditional. The SCU power mode register is replaced by a custom register on ECX-2000. Rather than read the number of cores from the SCU, just hardcode it to 4. This removes one use of SCU and removes the need for the SCU to be statically mapped. The cpu initialization will ultimately come from DT. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-highbank/highbank.c')
-rw-r--r--arch/arm/mach-highbank/highbank.c21
1 files changed, 5 insertions, 16 deletions
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 40e36a50304c..3da921a1a7f6 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -28,30 +28,19 @@
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
-#include <asm/smp_scu.h>
#include <asm/smp_twd.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include "core.h"
#include "sysregs.h"
void __iomem *sregs_base;
-
-#define HB_SCU_VIRT_BASE 0xfee00000
-void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
-
-static struct map_desc scu_io_desc __initdata = {
- .virtual = HB_SCU_VIRT_BASE,
- .pfn = 0, /* run-time */
- .length = SZ_4K,
- .type = MT_DEVICE,
-};
+void __iomem *scu_base_addr;
static void __init highbank_scu_map_io(void)
{
@@ -60,13 +49,11 @@ static void __init highbank_scu_map_io(void)
/* Get SCU base */
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
- scu_io_desc.pfn = __phys_to_pfn(base);
- iotable_init(&scu_io_desc, 1);
+ scu_base_addr = ioremap(base, SZ_4K);
}
static void __init highbank_map_io(void)
{
- highbank_scu_map_io();
highbank_lluart_map_io();
}
@@ -99,6 +86,9 @@ static void __init highbank_init_irq(void)
{
of_irq_init(irq_match);
+ if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
+ highbank_scu_map_io();
+
#ifdef CONFIG_CACHE_L2X0
/* Enable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x1);
@@ -145,7 +135,6 @@ static struct sys_timer highbank_timer = {
static void highbank_power_off(void)
{
hignbank_set_pwr_shutdown();
- scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
while (1)
cpu_do_idle();