path: root/arch/arm/mach-highbank/highbank.c
diff options
authorTaras Kondratiuk <taras.kondratiuk@linaro.org>2014-01-10 01:27:08 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-01-12 14:15:27 +0000
commitb25f3e1c358434bf850220e04f28eebfc45eb634 (patch)
tree5b72a6f960fad442b71df141d415eaa8a592c4e8 /arch/arm/mach-highbank/highbank.c
parentARM: 7939/1: traps: fix opcode endianness when read from user memory (diff)
ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling
Kexec disables outer cache before jumping to reboot code, but it doesn't flush it explicitly. Flush is done implicitly inside of l2x0_disable(). But some SoC's override default .disable handler and don't flush cache. This may lead to a corrupted memory during Kexec reboot on these platforms. This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable() handlers to make it consistent with default l2x0_disable(). Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-highbank/highbank.c')
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index b3d7e5634b83..ae171506cb06 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -50,6 +50,7 @@ static void __init highbank_scu_map_io(void)
static void highbank_l2x0_disable(void)
+ outer_flush_all();
/* Disable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x0);