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authorAnson Huang <b20788@freescale.com>2014-09-17 11:11:45 +0800
committerShawn Guo <shawn.guo@linaro.org>2014-11-23 14:56:17 +0800
commitec336b284136610a43c9daac56d66b20d43ddf7b (patch)
tree83577860847dac802631c097be8aefdd8b28ac96 /arch/arm/mach-imx/common.h
parentMerge tag 'imx-fixes-3.18-2' into imx/soc (diff)
downloadlinux-dev-ec336b284136610a43c9daac56d66b20d43ddf7b.tar.xz
linux-dev-ec336b284136610a43c9daac56d66b20d43ddf7b.zip
ARM: imx: replace cpu type check with ddr type check
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/common.h')
-rw-r--r--arch/arm/mach-imx/common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1dabf435c592..23c84e67a56d 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -116,6 +116,7 @@ void imx_anatop_post_resume(void);
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
+int imx_mmdc_get_ddr_type(void);
void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);