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| author |   Anson Huang <b20788@freescale.com> | 2014-06-23 16:42:43 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawn.guo@freescale.com> | 2014-07-18 16:11:30 +0800 |
| commit | dfea953ae221111c14d2fcfebad7b1973a0f49bd (patch) | |
| tree | 08b6f64b00c0b058a8c05017c8a6c233d8985131 /arch/arm/mach-imx/cpuidle-imx6q.c | |
| parent | ARM: imx6qdl: switch to use macro for clock ID (diff) | |
| download | linux-dev-dfea953ae221111c14d2fcfebad7b1973a0f49bd.tar.xz linux-dev-dfea953ae221111c14d2fcfebad7b1973a0f49bd.zip | |
ARM: imx: mem bit must be cleared before entering DSM mode
According to hardware design, mem bit must be clear before
entering DSM mode, as ARM core will be power gated in DSM mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/cpuidle-imx6q.c')
| -rw-r--r-- | arch/arm/mach-imx/cpuidle-imx6q.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index fc0bb1eafee3..10844d3bb926 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -71,7 +71,7 @@ int __init imx6q_cpuidle_init(void) imx_scu_standby_enable(); /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ - imx6q_set_int_mem_clk_lpm(); + imx6q_set_int_mem_clk_lpm(true); return cpuidle_register(&imx6q_cpuidle_driver, NULL); } |