diff options
| author |   Roland Stigge <stigge@antcom.de> | 2012-07-01 21:06:44 +0200 |
|---|---|---|
| committer | Roland Stigge <stigge@antcom.de> | 2012-07-01 21:06:44 +0200 |
| commit | 5df5d01dd04ce0dde58e305dd258c7e54f079e65 (patch) | |
| tree | 4f2bb93f12b64e2039e1c8f1287402a0057b1f22 /arch/arm/mach-lpc32xx | |
| parent | ARM: LPC32xx: Move i2s1 dma enabling to clock.c (diff) | |
| download | linux-dev-5df5d01dd04ce0dde58e305dd258c7e54f079e65.tar.xz linux-dev-5df5d01dd04ce0dde58e305dd258c7e54f079e65.zip | |
ARM: LPC32xx: Init MMC via clock
This patch moves MMC/SD controller initialization from the board specific file
phy3250.c to clock.c.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Diffstat (limited to 'arch/arm/mach-lpc32xx')
| -rw-r--r-- | arch/arm/mach-lpc32xx/clock.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-lpc32xx/phy3250.c | 5 |
2 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index e8d315e6db09..345c28d5615b 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -812,11 +812,13 @@ static int mmc_onoff_enable(struct clk *clk, int enable) u32 tmp; tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & - ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN); /* If rate is 0, disable clock */ if (enable != 0) - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | + LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index c1aabfcbde49..5be2cbfb4d99 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -262,11 +262,6 @@ static void __init lpc3250_machine_init(void) lpc32xx_serial_init(); - tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | - LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; - __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); - /* Test clock needed for UDA1380 initial init */ __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, |