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| author |   Vegard Nossum <vegard.nossum@gmail.com> | 2009-06-15 15:50:49 +0200 |
|---|---|---|
| committer | Vegard Nossum <vegard.nossum@gmail.com> | 2009-06-15 15:50:49 +0200 |
| commit | 722f2a6c87f34ee0fd0130a8cf45f81e0705594a (patch) | |
| tree | 50b054df34d2731eb0ba0cf1a6c27e43e7eed428 /arch/arm/mach-mmp/include/mach/regs-apbc.h | |
| parent | signal: fix __send_signal() false positive kmemcheck warning (diff) | |
| parent | Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-next (diff) | |
| download | linux-dev-722f2a6c87f34ee0fd0130a8cf45f81e0705594a.tar.xz linux-dev-722f2a6c87f34ee0fd0130a8cf45f81e0705594a.zip | |
Merge commit 'linus/master' into HEAD
Conflicts:
MAINTAINERS
Signed-off-by: Vegard Nossum <vegard.nossum@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp/include/mach/regs-apbc.h')
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apbc.h | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index c6b8c9dc2026..98ccbee4bd0c 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -22,8 +22,10 @@ #define APBC_PXA168_UART1 APBC_REG(0x000) #define APBC_PXA168_UART2 APBC_REG(0x004) #define APBC_PXA168_GPIO APBC_REG(0x008) -#define APBC_PXA168_PWM0 APBC_REG(0x00c) -#define APBC_PXA168_PWM1 APBC_REG(0x010) +#define APBC_PXA168_PWM1 APBC_REG(0x00c) +#define APBC_PXA168_PWM2 APBC_REG(0x010) +#define APBC_PXA168_PWM3 APBC_REG(0x014) +#define APBC_PXA168_PWM4 APBC_REG(0x018) #define APBC_PXA168_SSP1 APBC_REG(0x01c) #define APBC_PXA168_SSP2 APBC_REG(0x020) #define APBC_PXA168_RTC APBC_REG(0x028) @@ -48,10 +50,10 @@ #define APBC_PXA910_UART0 APBC_REG(0x000) #define APBC_PXA910_UART1 APBC_REG(0x004) #define APBC_PXA910_GPIO APBC_REG(0x008) -#define APBC_PXA910_PWM0 APBC_REG(0x00c) -#define APBC_PXA910_PWM1 APBC_REG(0x010) -#define APBC_PXA910_PWM2 APBC_REG(0x014) -#define APBC_PXA910_PWM3 APBC_REG(0x018) +#define APBC_PXA910_PWM1 APBC_REG(0x00c) +#define APBC_PXA910_PWM2 APBC_REG(0x010) +#define APBC_PXA910_PWM3 APBC_REG(0x014) +#define APBC_PXA910_PWM4 APBC_REG(0x018) #define APBC_PXA910_SSP1 APBC_REG(0x01c) #define APBC_PXA910_SSP2 APBC_REG(0x020) #define APBC_PXA910_IPC APBC_REG(0x024) |