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| author |   David Brown <davidb@codeaurora.org> | 2011-01-07 10:20:49 -0800 |
|---|---|---|
| committer | David Brown <davidb@codeaurora.org> | 2011-01-21 15:27:50 -0800 |
| commit | 8c27e6f305242ffab0c88eed5dea8394b8ce86d0 (patch) | |
| tree | 1fdcfc10f74a18883848b7273edd9f7e01cbcefe /arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | |
| parent | msm: Add CPU queries (diff) | |
| download | linux-dev-8c27e6f305242ffab0c88eed5dea8394b8ce86d0.tar.xz linux-dev-8c27e6f305242ffab0c88eed5dea8394b8ce86d0.zip | |
msm: Generalize timer register mappings
Allow the timer register to be determined dynamically instead of at
compile time. Use common virtual addresses for the registers across
all MSM chips, and select the register mappings based on the detected
CPU.
Signed-off-by: David Brown <davidb@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm/include/mach/msm_iomap-8x60.h')
| -rw-r--r-- | arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index a54e33b0882e..d5482d65bb37 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. * Author: Brian Swetland <swetland@google.com> * * This software is licensed under the terms of the GNU General Public @@ -58,16 +58,11 @@ #define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) #define MSM_SHARED_RAM_SIZE SZ_1M -#define MSM_TMR_BASE IOMEM(0xF0200000) -#define MSM_TMR_PHYS 0x02000000 -#define MSM_TMR_SIZE SZ_4K +#define MSM8X60_TMR_PHYS 0x02000000 +#define MSM8X60_TMR_SIZE SZ_4K -#define MSM_TMR0_BASE IOMEM(0xF0201000) -#define MSM_TMR0_PHYS 0x02040000 -#define MSM_TMR0_SIZE SZ_4K - -#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) -#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) +#define MSM8X60_TMR0_PHYS 0x02040000 +#define MSM8X60_TMR0_SIZE SZ_4K #define MSM_IOMMU_JPEGD_PHYS 0x07300000 #define MSM_IOMMU_JPEGD_SIZE SZ_1M |