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author | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2012-09-12 11:14:33 -0400 |
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committer | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2012-09-12 11:14:33 -0400 |
commit | 25a765b7f05cb8460fa01b54568894b20e184862 (patch) | |
tree | 0b56db57b4d9f912393ab303c269e0fe6cdf8635 /arch/arm/mach-omap2/clock_common_data.c | |
parent | xen/privcmd: return -EFAULT on error (diff) | |
parent | x86: Document x86_init.paging.pagetable_init() (diff) | |
download | linux-dev-25a765b7f05cb8460fa01b54568894b20e184862.tar.xz linux-dev-25a765b7f05cb8460fa01b54568894b20e184862.zip |
Merge branch 'x86/platform' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into stable/for-linus-3.7
* 'x86/platform' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (9690 commits)
x86: Document x86_init.paging.pagetable_init()
x86: xen: Cleanup and remove x86_init.paging.pagetable_setup_done()
x86: Move paging_init() call to x86_init.paging.pagetable_init()
x86: Rename pagetable_setup_start() to pagetable_init()
x86: Remove base argument from x86_init.paging.pagetable_setup_start
Linux 3.6-rc5
HID: tpkbd: work even if the new Lenovo Keyboard driver is not configured
Remove user-triggerable BUG from mpol_to_str
xen/pciback: Fix proper FLR steps.
uml: fix compile error in deliver_alarm()
dj: memory scribble in logi_dj
Fix order of arguments to compat_put_time[spec|val]
xen: Use correct masking in xen_swiotlb_alloc_coherent.
xen: fix logical error in tlb flushing
xen/p2m: Fix one-off error in checking the P2M tree directory.
powerpc: Don't use __put_user() in patch_instruction
powerpc: Make sure IPI handlers see data written by IPI senders
powerpc: Restore correct DSCR in context switch
powerpc: Fix DSCR inheritance in copy_thread()
powerpc: Keep thread.dscr and thread.dscr_inherit in sync
...
Diffstat (limited to 'arch/arm/mach-omap2/clock_common_data.c')
-rw-r--r-- | arch/arm/mach-omap2/clock_common_data.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c index 6424d46be14a..b9f3ba68148c 100644 --- a/arch/arm/mach-omap2/clock_common_data.c +++ b/arch/arm/mach-omap2/clock_common_data.c @@ -43,3 +43,80 @@ const struct clksel_rate dsp_ick_rates[] = { { .div = 3, .val = 3, .flags = RATE_IN_243X }, { .div = 0 }, }; + + +/* clksel_rate blocks shared between OMAP44xx and AM33xx */ + +const struct clksel_rate div_1_0_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 0 }, +}; + +const struct clksel_rate div_1_1_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 0 }, +}; + +const struct clksel_rate div_1_2_rates[] = { + { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 0 }, +}; + +const struct clksel_rate div_1_3_rates[] = { + { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 0 }, +}; + +const struct clksel_rate div_1_4_rates[] = { + { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 0 }, +}; + +const struct clksel_rate div31_1to31_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX }, + { .div = 0 }, +}; + +/* Clocks shared between various OMAP SoCs */ + +struct clk virt_19200000_ck = { + .name = "virt_19200000_ck", + .ops = &clkops_null, + .rate = 19200000, +}; + +struct clk virt_26000000_ck = { + .name = "virt_26000000_ck", + .ops = &clkops_null, + .rate = 26000000, +}; |