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| author |   Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-03-19 19:29:41 +0530 |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2012-07-09 19:14:39 +0530 |
| commit | 283f708ca846903ee045e9f9374d627f7b47a711 (patch) | |
| tree | cfd5db40a28e4c02ed0696fbd63945157e73020d /arch/arm/mach-omap2/omap-smp.c | |
| parent | ARM: OMAP5: Add the WakeupGen IP updates (diff) | |
| download | linux-dev-283f708ca846903ee045e9f9374d627f7b47a711.tar.xz linux-dev-283f708ca846903ee045e9f9374d627f7b47a711.zip | |
ARM: OMAP5: Add SMP support
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap-smp.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap-smp.c | 35 |
1 files changed, 23 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index badfe398038e..7d118b9bdd5f 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -33,6 +33,12 @@ #include "common.h" #include "clockdomain.h" +#define CPU_MASK 0xff0ffff0 +#define CPU_CORTEX_A9 0x410FC090 +#define CPU_CORTEX_A15 0x410FC0F0 + +#define OMAP5_CORE_COUNT 0x2 + /* SCU base address */ static void __iomem *scu_base; @@ -133,7 +139,6 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init wakeup_secondary(void) { void __iomem *base = omap_get_wakeupgen_base(); - /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing @@ -162,16 +167,21 @@ static void __init wakeup_secondary(void) */ void __init smp_init_cpus(void) { - unsigned int i, ncores; - - /* - * Currently we can't call ioremap here because - * SoC detection won't work until after init_early. - */ - scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); - BUG_ON(!scu_base); - - ncores = scu_get_core_count(scu_base); + unsigned int i = 0, ncores = 1, cpu_id; + + /* Use ARM cpuid check here, as SoC detection will not work so early */ + cpu_id = read_cpuid(CPUID_ID) & CPU_MASK; + if (cpu_id == CPU_CORTEX_A9) { + /* + * Currently we can't call ioremap here because + * SoC detection won't work until after init_early. + */ + scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); + BUG_ON(!scu_base); + ncores = scu_get_core_count(scu_base); + } else if (cpu_id == CPU_CORTEX_A15) { + ncores = OMAP5_CORE_COUNT; + } /* sanity check */ if (ncores > nr_cpu_ids) { @@ -193,6 +203,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * Initialise the SCU and wake up the secondary core using * wakeup_secondary(). */ - scu_enable(scu_base); + if (scu_base) + scu_enable(scu_base); wakeup_secondary(); } |