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author | Kukjin Kim <kgene.kim@samsung.com> | 2012-02-06 09:38:19 +0900 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-03-03 07:47:38 +0900 |
commit | 85fd6d63bf2927b9da7ab1b0d46723bfdb13808c (patch) | |
tree | 7033ac06e365209b09ba4b97eba0cf2f7ceb3312 /arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h | |
parent | ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX (diff) | |
download | linux-dev-85fd6d63bf2927b9da7ab1b0d46723bfdb13808c.tar.xz linux-dev-85fd6d63bf2927b9da7ab1b0d46723bfdb13808c.zip |
ARM: S3C2410: move mach-s3c2410/* into mach-s3c24xx/
This patch moves S3C2410 stuff into mach-s3c24xx/ directory
so that we can merge the s3c24 series' directories to the
just one mach-s3c24xx/ directory.
And this patch is including following.
- re-ordered alphabetically by option text at Kconfig and Makefile
- removed unused option, MACH_N35
- fixed duplcated option name, S3C2410_DMA to S3C24XX_DMA which is
in plat-s3c24xx/
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h')
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h deleted file mode 100644 index fb6352515090..000000000000 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h +++ /dev/null @@ -1,48 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2412 memory register definitions -*/ - -#ifndef __ASM_ARM_REGS_S3C2412_MEM -#define __ASM_ARM_REGS_S3C2412_MEM - -#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) -#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) - -#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x)) -#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o))) - -#define S3C2412_BANKCFG S3C2412_MEMREG(0x00) -#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04) -#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08) -#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C) - -#define S3C2412_REFRESH S3C2412_MEMREG(0x10) -#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14) - -/* EBI control registers */ - -#define S3C2412_EBI_PR S3C2412_EBIREG(0x00) -#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04) - -/* SSMC control registers */ - -#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00) -#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04) -#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08) -#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C) -#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10) -#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14) -#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18) -#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C) - -#endif /* __ASM_ARM_REGS_S3C2412_MEM */ |