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authorArnd Bergmann <arnd@arndb.de>2012-03-19 20:52:33 +0000
committerArnd Bergmann <arnd@arndb.de>2012-03-20 10:07:48 +0000
commitbde755679a3ba5af0d16231f8532e8373c5e2ecc (patch)
tree782fa01306ada3e084bd3c47ea1af378b97c0e16 /arch/arm/mach-s5p64x0/clock.c
parentMerge branch 'renesas/soc' into next/soc (diff)
parentARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver (diff)
downloadlinux-dev-bde755679a3ba5af0d16231f8532e8373c5e2ecc.tar.xz
linux-dev-bde755679a3ba5af0d16231f8532e8373c5e2ecc.zip
Merge branch 'samsung/cleanup-exynos-clock' into next/soc
Conflicts: arch/arm/mach-exynos/clock-exynos4.c arch/arm/mach-exynos/clock.c The cleanup moves the exynos4 clock implementation away, while the other branch modifies the file with the old name. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-s5p64x0/clock.c')
-rw-r--r--arch/arm/mach-s5p64x0/clock.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index 241d0e645c85..57e718957ef3 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -73,7 +73,7 @@ static const u32 clock_table[][3] = {
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
};
-unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
+static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv;
@@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
return rate / (clkdiv + 1);
}
-unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
+ unsigned long rate)
{
u32 iter;
@@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
return clock_table[ARRAY_SIZE(clock_table) - 1][0];
}
-int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
+static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
{
u32 round_tmp;
u32 iter;
@@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
-struct clk_ops s5p64x0_clkarm_ops = {
+static struct clk_ops s5p64x0_clkarm_ops = {
.get_rate = s5p64x0_armclk_get_rate,
.set_rate = s5p64x0_armclk_set_rate,
.round_rate = s5p64x0_armclk_round_rate,
@@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = {
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
};
-struct clk *clkset_hclk_low_list[] = {
+static struct clk *clkset_hclk_low_list[] = {
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};