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authorColin Cross <ccross@android.com>2011-02-12 18:24:32 -0800
committerColin Cross <ccross@android.com>2011-02-21 00:16:47 -0800
commit9743b38969790d33b077ab80b175ea63a0398703 (patch)
tree5f264886b0fef728534ff6a29a9d82579edb6111 /arch/arm/mach-tegra/clock.h
parentARM: tegra: cpufreq: Adjust memory frequency with cpu frequency (diff)
downloadlinux-dev-9743b38969790d33b077ab80b175ea63a0398703.tar.xz
linux-dev-9743b38969790d33b077ab80b175ea63a0398703.zip
ARM: tegra: clock: Add function to set SDMMC tap delay
The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/clock.h')
-rw-r--r--arch/arm/mach-tegra/clock.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index ebe6ea8b0575..688316abc64e 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -155,5 +155,6 @@ int clk_reparent(struct clk *c, struct clk *parent);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
unsigned long clk_get_rate_locked(struct clk *c);
int clk_set_rate_locked(struct clk *c, unsigned long rate);
+void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
#endif