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| author |   Joseph Lo <josephl@nvidia.com> | 2013-07-03 17:50:40 +0800 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2013-07-19 10:08:06 -0600 |
| commit | ccea4bc654a9d5330c4488acadc3abfa4ea7ebbf (patch) | |
| tree | af6af4a789343de0b69fdd3a7cf05e7257a54728 /arch/arm/mach-tegra/flowctrl.h | |
| parent | ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15 (diff) | |
| download | linux-dev-ccea4bc654a9d5330c4488acadc3abfa4ea7ebbf.tar.xz linux-dev-ccea4bc654a9d5330c4488acadc3abfa4ea7ebbf.zip | |
ARM: tegra: add low level code for Tegra114 cluster power down
When the CPU cluster power down, the vGIC is powered down too. The
flow controller needs to monitor the legacy interrupt controller to
wake up CPU. So setting up the appropriate wake up event in flow
controller.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/flowctrl.h')
| -rw-r--r-- | arch/arm/mach-tegra/flowctrl.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index e56a950920f6..de0acb9ee323 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -28,6 +28,8 @@ #define FLOW_CTRL_SCLK_RESUME (1 << 27) #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) +#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) #define FLOW_CTRL_CPU0_CSR 0x8 |