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| author |   Olof Johansson <olof@lixom.net> | 2011-10-17 16:39:24 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-02-06 18:24:59 -0800 |
| commit | dee47183301983139fd0ed784d0defe0ba08f8f6 (patch) | |
| tree | a6c0f2215cf20b1394d35325e2041d638e9e5665 /arch/arm/mach-tegra/fuse.c | |
| parent | ARM: tegra: fuse: add functions to access chip revision (diff) | |
| download | linux-dev-dee47183301983139fd0ed784d0defe0ba08f8f6.tar.xz linux-dev-dee47183301983139fd0ed784d0defe0ba08f8f6.zip | |
ARM: tegra: fuse: add bct strapping reading
This is used by the memory setup code to pick the right memory
timing table, if needed.
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/fuse.c')
| -rw-r--r-- | arch/arm/mach-tegra/fuse.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index b1895c53ed60..17fdd4086e6f 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -35,6 +35,17 @@ int tegra_cpu_process_id; int tegra_core_process_id; enum tegra_revision tegra_revision; +/* The BCT to use at boot is specified by board straps that can be read + * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. + */ +int tegra_bct_strapping; + +#define STRAP_OPT 0x008 +#define GMI_AD0 (1 << 4) +#define GMI_AD1 (1 << 5) +#define RAM_ID_MASK (GMI_AD0 | GMI_AD1) +#define RAM_CODE_SHIFT 4 + static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { [TEGRA_REVISION_UNKNOWN] = "unknown", [TEGRA_REVISION_A01] = "A01", @@ -93,6 +104,9 @@ void tegra_init_fuse(void) reg = tegra_fuse_readl(FUSE_SPARE_BIT); tegra_core_process_id = (reg >> 12) & 3; + reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); + tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; + tegra_revision = tegra_get_revision(); pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", |