diff options
| author |   Joseph Lo <josephl@nvidia.com> | 2012-10-31 17:41:21 +0800 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2012-11-15 15:09:22 -0700 |
| commit | d552920a02759cdc45d8507868de10ac2f5b9a18 (patch) | |
| tree | 2c3c5f805e1657f64088631e63c145cc43739608 /arch/arm/mach-tegra/pm.h | |
| parent | ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function (diff) | |
| download | linux-dev-d552920a02759cdc45d8507868de10ac2f5b9a18.tar.xz linux-dev-d552920a02759cdc45d8507868de10ac2f5b9a18.zip | |
ARM: tegra30: cpuidle: add powered-down state for CPU0
This is a power gating idle mode. It support power gating vdd_cpu rail
after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can
enter this state only when all secondary CPU is offline. We need to take
care and make sure whole secondary CPUs were offline and checking the
CPU power gate status. After that, the CPU0 can go into "powered-down"
state safely. Then shut off the CPU rail.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Base on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index bcfc45faad78..512345c9eec3 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -27,4 +27,7 @@ void restore_cpu_arch_register(void); void tegra_clear_cpu_in_lp2(int phy_cpu_id); bool tegra_set_cpu_in_lp2(int phy_cpu_id); +void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time); +extern void (*tegra_tear_down_cpu)(void); + #endif /* _MACH_TEGRA_PM_H_ */ |