diff options
| author |   Joseph Lo <josephl@nvidia.com> | 2013-02-19 18:16:13 +0800 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2013-03-11 14:29:22 -0600 |
| commit | b095ae2b9f35c838257786de27e550d62bd7c763 (patch) | |
| tree | 52c81ea41fce50f8db6c7732a3d4743182fab57e /arch/arm/mach-tegra/reset-handler.S | |
| parent | clk: tegra: No 7.1 super clk dividers on Tegra20 (diff) | |
| download | linux-dev-b095ae2b9f35c838257786de27e550d62bd7c763.tar.xz linux-dev-b095ae2b9f35c838257786de27e550d62bd7c763.zip | |
ARM: tegra: don't unlock MMIO access to DBGLAR
There is no need to unlock MMIO access to the DBGLAR all the time. Doing
so may even cause problems if a SW bug causes writes to that MMIO region.
Cortex-A15 processors do not support the CP14 register write the code
currently uses to unlock the DBGLAR; the instruction throws an undefined
instruction exceptions. This prevents tegra_secondary_startup() from
executing on Tegra114, and hence prevents SMP.
Remove the code that unlocks this access.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset-handler.S')
| -rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index ff7b45c6c2a0..1676aba5e7b8 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -41,9 +41,6 @@ */ ENTRY(tegra_resume) bl v7_invalidate_l1 - /* Enable coresight */ - mov32 r0, 0xC5ACCE55 - mcr p14, 0, r0, c7, c12, 6 cpu_id r0 cmp r0, #0 @ CPU0? |