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| author |   Alexandre Courbot <acourbot@nvidia.com> | 2013-11-24 15:30:51 +0900 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2013-12-13 12:50:31 -0700 |
| commit | 265c89c994611e75943563e9b741cb8ae04a43af (patch) | |
| tree | 6652e169a599dc212a1bed55ff2feec095c4f288 /arch/arm/mach-tegra/reset.c | |
| parent | ARM: tegra: split setting of CPU reset handler (diff) | |
| download | linux-dev-265c89c994611e75943563e9b741cb8ae04a43af.tar.xz linux-dev-265c89c994611e75943563e9b741cb8ae04a43af.zip | |
ARM: tegra: set CPU reset handler using firmware
Use a firmware operation to set the CPU reset handler and only resort to
doing it ourselves if there is none defined.
This supports the booting of secondary CPUs on devices using a TrustZone
secure monitor.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset.c')
| -rw-r--r-- | arch/arm/mach-tegra/reset.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 17c4b6d6b498..146fe8e0ae7c 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -21,6 +21,7 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/firmware.h> #include "iomap.h" #include "irammap.h" @@ -65,6 +66,7 @@ static void __init tegra_cpu_reset_handler_enable(void) void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); const u32 reset_address = TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset; + int err; BUG_ON(is_enabled); BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); @@ -72,9 +74,18 @@ static void __init tegra_cpu_reset_handler_enable(void) memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, tegra_cpu_reset_handler_size); - tegra_cpu_reset_handler_set(reset_address); - - is_enabled = true; + err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); + switch (err) { + case -ENOSYS: + tegra_cpu_reset_handler_set(reset_address); + /* pass-through */ + case 0: + is_enabled = true; + break; + default: + pr_crit("Cannot set CPU reset handler: %d\n", err); + BUG(); + } } void __init tegra_cpu_reset_handler_init(void) |