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| author |   Joseph Lo <josephl@nvidia.com> | 2013-01-03 14:42:59 +0800 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2013-01-28 10:21:44 -0700 |
| commit | 57886616ca7bff844a6427436d0c8faf74653f73 (patch) | |
| tree | 4c353be72a7f266727320189e8e91965b93fa0b0 /arch/arm/mach-tegra/sleep-tegra30.S | |
| parent | ARM: tegra30: fix power up sequence for boot_secondary (diff) | |
| download | linux-dev-57886616ca7bff844a6427436d0c8faf74653f73.tar.xz linux-dev-57886616ca7bff844a6427436d0c8faf74653f73.zip | |
ARM: tegra: update the cache maintenance order for CPU shutdown
Updating the cache maintenance order before CPU shutdown when doing CPU
hotplug.
The old order:
* clean L1 by flush_cache_all
* exit SMP
* CPU shutdown
Adapt to:
* disable L1 data cache by clear C bit
* clean L1 by v7_flush_dcache_louis
* exit SMP
* CPU shutdown
For CPU hotplug case, it's no need to do "flush_cache_all". And we should
disable L1 data cache before clean L1 data cache. Then leaving the SMP
coherency.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-tegra30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-tegra30.S | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 562a8e7e413d..63a15bd9b653 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -32,9 +32,6 @@ * Should never return. */ ENTRY(tegra30_hotplug_shutdown) - /* Turn off SMP coherency */ - exit_smp r4, r5 - /* Powergate this CPU */ mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN bl tegra30_cpu_shutdown |