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author | 2018-11-25 00:13:46 +0300 | |
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committer | 2019-01-16 13:21:45 +0100 | |
commit | 82cdfc382b940b441e93188507c5ae68f9582e3d (patch) | |
tree | 387ca6b3cbb2323132a75857664d27c0172233b7 /arch/arm/mach-tegra/sleep-tegra30.S | |
parent | Linux 5.0-rc1 (diff) | |
download | linux-dev-82cdfc382b940b441e93188507c5ae68f9582e3d.tar.xz linux-dev-82cdfc382b940b441e93188507c5ae68f9582e3d.zip |
ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+
The memory interface configuration and re-calibration interval are left
unassigned on resume from LP1 because these registers are shadowed and
require latching after being adjusted.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-tegra30.S')
-rw-r--r-- | arch/arm/mach-tegra/sleep-tegra30.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index dd4a67dabd91..efc6493b61f3 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -521,6 +521,8 @@ zcal_done: ldr r1, [r5, #0x0] @ restore EMC_CFG str r1, [r0, #EMC_CFG] + emc_timing_update r1, r0 + /* Tegra114 had dual EMC channel, now config the other one */ cmp r10, #TEGRA114 bne __no_dual_emc_chanl |