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| author |   Joseph Lo <josephl@nvidia.com> | 2012-11-13 10:04:48 +0800 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2012-11-15 15:09:22 -0700 |
| commit | 29a0e7beab8e05be53d5b9c050253a4dc417041e (patch) | |
| tree | eddaa429e909f209cb0628b0733e0ade8e277fd0 /arch/arm/mach-tegra/sleep.S | |
| parent | ARM: tegra30: cpuidle: add powered-down state for CPU0 (diff) | |
| download | linux-dev-29a0e7beab8e05be53d5b9c050253a4dc417041e.tar.xz linux-dev-29a0e7beab8e05be53d5b9c050253a4dc417041e.zip | |
ARM: tegra: retain L2 content over CPU suspend/resume
The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable L2 before
the MMU is enabled. But the L2 controller is in the same power domain
with the CPU cluster. We need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 88f4de986a52..26afa7cbed11 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -27,6 +27,7 @@ #include <asm/assembler.h> #include <asm/cache.h> #include <asm/cp15.h> +#include <asm/hardware/cache-l2x0.h> #include "iomap.h" @@ -98,6 +99,12 @@ ENTRY(tegra_shut_off_mmu) dsb mcr p15, 0, r3, c1, c0, 0 isb +#ifdef CONFIG_CACHE_L2X0 + /* Disable L2 cache */ + mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 + mov r5, #0 + str r5, [r4, #L2X0_CTRL] +#endif mov pc, r0 ENDPROC(tegra_shut_off_mmu) .popsection |