diff options
| author |   Joseph Lo <josephl@nvidia.com> | 2012-10-31 17:41:17 +0800 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2012-11-15 15:09:21 -0700 |
| commit | d457ef358f3c7179c428becda45b1dfd2b8cf98a (patch) | |
| tree | 90299ea88a7fb8ebe02cb2cd45160db13afe6775 /arch/arm/mach-tegra/sleep.S | |
| parent | ARM: tegra: cpuidle: add CPU resume function (diff) | |
| download | linux-dev-d457ef358f3c7179c428becda45b1dfd2b8cf98a.tar.xz linux-dev-d457ef358f3c7179c428becda45b1dfd2b8cf98a.zip | |
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs
This supports power-gated idle on secondary CPUs for Tegra30. The
secondary CPUs can go into powered-down state independently. When
CPU goes into this state, it saves it's contexts and puts itself
to flow controlled WFI state. After that, it will been power gated.
Be aware of that, you may see the legacy power state "LP2" in the
code which is exactly the same meaning of "CPU power down".
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 08e9481c049e..91548a77dd95 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -25,9 +25,38 @@ #include <linux/linkage.h> #include <asm/assembler.h> +#include <asm/cp15.h> #include "iomap.h" #include "flowctrl.h" #include "sleep.h" +#ifdef CONFIG_PM_SLEEP +/* + * tegra_disable_clean_inv_dcache + * + * disable, clean & invalidate the D-cache + * + * Corrupted registers: r1-r3, r6, r8, r9-r11 + */ +ENTRY(tegra_disable_clean_inv_dcache) + stmfd sp!, {r0, r4-r5, r7, r9-r11, lr} + dmb @ ensure ordering + + /* Disable the D-cache */ + mrc p15, 0, r2, c1, c0, 0 + bic r2, r2, #CR_C + mcr p15, 0, r2, c1, c0, 0 + isb + + /* Flush the D-cache */ + bl v7_flush_dcache_louis + + /* Trun off coherency */ + exit_smp r4, r5 + + ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} +ENDPROC(tegra_disable_clean_inv_dcache) + +#endif |