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| author |   Joseph Lo <josephl@nvidia.com> | 2013-05-20 18:39:25 +0800 |
|---|---|---|
| committer |   Stephen Warren <swarren@nvidia.com> | 2013-05-22 15:19:22 -0600 |
| commit | f6d06f33664756cfa8bce3494e586be32b213bdd (patch) | |
| tree | daeb1a5839ece049ef3159cf07c5a2b60647a9a9 /arch/arm/mach-tegra/sleep.S | |
| parent | ARM: tegra: add an assembly marco to check Tegra SoC ID (diff) | |
| download | linux-dev-f6d06f33664756cfa8bce3494e586be32b213bdd.tar.xz linux-dev-f6d06f33664756cfa8bce3494e586be32b213bdd.zip | |
ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9
For supporting single image on all Tegra series, we need to skip some HW
support code for Cortex-A9 only.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 364d84523fba..9daaef26b0f6 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu) isb #ifdef CONFIG_CACHE_L2X0 /* Disable L2 cache */ - mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 - mov r5, #0 - str r5, [r4, #L2X0_CTRL] + check_cpu_part_num 0xc09, r9, r10 + movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) + movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) + moveq r5, #0 + streq r5, [r4, #L2X0_CTRL] #endif mov pc, r0 ENDPROC(tegra_shut_off_mmu) |