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| author |   Thomas Gleixner <tglx@linutronix.de> | 2012-05-08 14:07:48 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2012-05-08 14:07:48 +0200 |
| commit | 67ba5293f705eb1d1b98710e5ccb0f615936a6fc (patch) | |
| tree | cdb4cfd94033b5c0f42eeb4de368802049880a12 /arch/arm/mm/abort-ev6.S | |
| parent | sh: Remove cpu_idle_wait() (diff) | |
| parent | tile: Use common threadinfo allocator (diff) | |
| download | linux-dev-67ba5293f705eb1d1b98710e5ccb0f615936a6fc.tar.xz linux-dev-67ba5293f705eb1d1b98710e5ccb0f615936a6fc.zip | |
Merge branch 'smp/threadalloc' into smp/hotplug
Reason: Pull in the separate branch which was created so arch/tile can
base further work on it.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mm/abort-ev6.S')
| -rw-r--r-- | arch/arm/mm/abort-ev6.S | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index ff1f7cc11f87..80741992a9fc 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -26,18 +26,23 @@ ENTRY(v6_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR /* - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). - * The test below covers all the write situations, including Java bytecodes + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. */ - bic r1, r1, #1 << 11 @ clear bit 11 of FSR +#ifdef CONFIG_ARM_ERRATA_326103 + ldr ip, =0x4107b36 + mrc p15, 0, r3, c0, c0, 0 @ get processor id + teq ip, r3, lsr #4 @ r0 ARM1136? + bne do_DataAbort tst r5, #PSR_J_BIT @ Java? + tsteq r5, #PSR_T_BIT @ Thumb? bne do_DataAbort - do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3 - ldreq r3, [r4] @ read aborted ARM instruction + bic r1, r1, #1 << 11 @ clear bit 11 of FSR + ldr r3, [r4] @ read aborted ARM instruction #ifdef CONFIG_CPU_ENDIAN_BE8 - reveq r3, r3 + rev r3, r3 #endif do_ldrd_abort tmp=ip, insn=r3 tst r3, #1 << 20 @ L = 0 -> write orreq r1, r1, #1 << 11 @ yes. +#endif b do_DataAbort |