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author | H. Peter Anvin <hpa@linux.intel.com> | 2012-01-19 12:56:50 -0800 |
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committer | H. Peter Anvin <hpa@linux.intel.com> | 2012-01-19 12:56:50 -0800 |
commit | 282f445a779ed76fca9884fe377bf56a3088b208 (patch) | |
tree | d9abcf526baee0100672851e0a8894c19e762a39 /arch/arm/mm/proc-xsc3.S | |
parent | x86, tsc: Fix SMI induced variation in quick_pit_calibrate() (diff) | |
parent | uml: fix compile for x86-64 (diff) | |
download | linux-dev-282f445a779ed76fca9884fe377bf56a3088b208.tar.xz linux-dev-282f445a779ed76fca9884fe377bf56a3088b208.zip |
Merge remote-tracking branch 'linus/master' into x86/urgent
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index abf0507a08ae..b0d57869da2d 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -105,6 +105,7 @@ ENTRY(cpu_xsc3_proc_fin) * loc: location to jump to for soft reset */ .align 5 + .pushsection .idmap.text, "ax" ENTRY(cpu_xsc3_reset) mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE msr cpsr_c, r1 @ reset CPSR @@ -119,6 +120,8 @@ ENTRY(cpu_xsc3_reset) @ already containing those two last instructions to survive. mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs mov pc, r0 +ENDPROC(cpu_xsc3_reset) + .popsection /* * cpu_xsc3_do_idle() |