aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-17 17:15:02 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-30 00:47:54 +0100
commit17f3f99fab43ad17ae1adfc724e5ebaca9635902 (patch)
treefc46cba3f2b5dd0dcf96b6d61ea2fbaa3af87e66 /arch/arm/mm
parentARM: l2c: provide enable method (diff)
downloadlinux-dev-17f3f99fab43ad17ae1adfc724e5ebaca9635902.tar.xz
linux-dev-17f3f99fab43ad17ae1adfc724e5ebaca9635902.zip
ARM: l2c: write auxctrl register before unlocking
We should write the auxillary control register before unlocking: the write may be necessary to enable non-secure access to the lock registers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-l2x0.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 2adb82e7f4b3..fc609550b7fa 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -92,10 +92,10 @@ static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
{
unsigned long flags;
- l2c_unlock(base, num_lock);
-
writel_relaxed(aux, base + L2X0_AUX_CTRL);
+ l2c_unlock(base, num_lock);
+
local_irq_save(flags);
__l2c_op_way(base + L2X0_INV_WAY);
writel_relaxed(0, base + sync_reg_offset);
@@ -368,12 +368,12 @@ static void l2x0_unlock(u32 cache_id)
static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock)
{
- /* Make sure that I&D is not locked down when starting */
- l2x0_unlock(readl_relaxed(base + L2X0_CACHE_ID));
-
/* l2x0 controller is disabled */
writel_relaxed(aux, base + L2X0_AUX_CTRL);
+ /* Make sure that I&D is not locked down when starting */
+ l2x0_unlock(readl_relaxed(base + L2X0_CACHE_ID));
+
l2x0_inv_all();
/* enable L2X0 */