diff options
| author |   Sascha Hauer <s.hauer@pengutronix.de> | 2010-02-04 14:45:41 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-02-04 15:56:34 +0100 |
| commit | 9cf945cbef42a4524b6a58486bd8bfb96640e97f (patch) | |
| tree | 777e8ead1904e7158901493b0c22314c2550dbfb /arch/arm/plat-mxc/ehci.c | |
| parent | i.MX ehci platform support: Some fixes (diff) | |
| download | linux-dev-9cf945cbef42a4524b6a58486bd8bfb96640e97f.tar.xz linux-dev-9cf945cbef42a4524b6a58486bd8bfb96640e97f.zip | |
i.MX27: Add USB control register access support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Daniel Mack <daniel@caiaq.de>
Diffstat (limited to 'arch/arm/plat-mxc/ehci.c')
| -rw-r--r-- | arch/arm/plat-mxc/ehci.c | 47 |
1 files changed, 46 insertions, 1 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 586b55dc2ab1..816a9cc60e5d 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -41,7 +41,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; - +#ifdef CONFIG_ARCH_MX3 if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); @@ -85,7 +85,52 @@ int mxc_set_usbcontrol(int port, unsigned int flags) USBCTRL_OTGBASE_OFFSET)); return 0; } +#endif /* CONFIG_ARCH_MX3 */ +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) { + /* On i.MX27 we can use the i.MX31 USBCTRL bits, they + * are identical + */ + v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + switch (port) { + case 0: /* OTG port */ + v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_OTG_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_OTG_PM_BIT; + break; + case 1: /* H1 port */ + v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H1_DT_BIT; + break; + case 2: /* H2 port */ + v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_H2_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H2_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H2_DT_BIT; + + break; + default: + return -EINVAL; + } + writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + return 0; + } +#endif /* CONFIG_MACH_MX27 */ printk(KERN_WARNING "%s() unable to setup USBCONTROL for this CPU\n", __func__); return -EINVAL; |