diff options
| author |   Yong Shen <yong.shen@freescale.com> | 2011-01-10 20:08:53 +0800 |
|---|---|---|
| committer |   Sascha Hauer <s.hauer@pengutronix.de> | 2011-01-11 10:07:14 +0100 |
| commit | b0a6ba5ffbb52b5e8fccd1a013e770e1b0af03ba (patch) | |
| tree | 6b2686389647254f255c5f9750e744a34b070b8f /arch/arm/plat-mxc/include | |
| parent | ARM i.MX27 3ds: Fix mc13783 regulator names (diff) | |
| download | linux-dev-b0a6ba5ffbb52b5e8fccd1a013e770e1b0af03ba.tar.xz linux-dev-b0a6ba5ffbb52b5e8fccd1a013e770e1b0af03ba.zip | |
ARM i.MX53 enable spi on EVK board
1. some macro definitions fix
2. add platform data for spi device
3. register spi clocks
Signed-off-by: Yong Shen <yong.shen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx53.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 340937f94e6f..d7a8e52181ea 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h @@ -56,7 +56,7 @@ #define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) #define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) -#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) +#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) #define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) #define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) @@ -117,12 +117,12 @@ #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) -#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) +#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) -#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) +#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) @@ -264,8 +264,8 @@ #define MX53_INT_UART3 33 #define MX53_INT_RESV34 34 #define MX53_INT_RESV35 35 -#define MX53_INT_CSPI1 36 -#define MX53_INT_CSPI2 37 +#define MX53_INT_ECSPI1 36 +#define MX53_INT_ECSPI2 37 #define MX53_INT_CSPI 38 #define MX53_INT_GPT 39 #define MX53_INT_EPIT1 40 |