diff options
| author |   Vaibhav Hiremath <hvaibhav@ti.com> | 2012-02-17 16:56:01 +0530 |
|---|---|---|
| committer |   Paul Walmsley <paul@pwsan.com> | 2012-04-05 02:59:32 -0600 |
| commit | 4ce107ccd714e54f7076aba585295421d30ad7f7 (patch) | |
| tree | 902dd32c555405c6d298b962e01308448f197c4f /arch/arm/plat-omap/include | |
| parent | ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status (diff) | |
| download | linux-dev-4ce107ccd714e54f7076aba585295421d30ad7f7.tar.xz linux-dev-4ce107ccd714e54f7076aba585295421d30ad7f7.zip | |
ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions
In the SYSC_TYPE1_XXX_MASK configuration, SYSC_XXX_SHIFT macro
is used which is not defined anywhere in the kernel.
Until now the build was going through successfully, since it
is not being used anywhere in kernel.
This bug got introduced by the commit
358f0e630d5409ab3837b86db3595560eae773b6 ("OMAP3: hwmod: support
to specify the offset position of various SYSCONFIG register bits.")
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/omap_hwmod.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 9e8e63d52aab..8070145ccb98 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -47,17 +47,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; * with the original PRCM protocol defined for OMAP2420 */ #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 -#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) +#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT) #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 -#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) +#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT) #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 -#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) +#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT) #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 -#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) +#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT) #define SYSC_TYPE1_SOFTRESET_SHIFT 1 -#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) +#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT) #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 -#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) +#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT) /* * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant |