diff options
| author |   Fernando Guzman Lugo <fernando.lugo@ti.com> | 2012-04-13 05:08:03 -0600 |
|---|---|---|
| committer |   Paul Walmsley <paul@pwsan.com> | 2012-04-13 05:08:03 -0600 |
| commit | d99de7f552fac43e24fd4fb8048d8f21abaea691 (patch) | |
| tree | 29437f2fd6b5f8516ce1cfe773b93b7bdab9c290 /arch/arm/plat-omap/include | |
| parent | Linux 3.4-rc2 (diff) | |
| download | linux-dev-d99de7f552fac43e24fd4fb8048d8f21abaea691.tar.xz linux-dev-d99de7f552fac43e24fd4fb8048d8f21abaea691.zip | |
ARM: OMAP2+: hwmod: add softreset delay field and OMAP4 data
Due to HW limitation, some IPs should not be accessed just after a
softreset. Since the current hwmod sequence is accessing the sysconfig
register just after the reset, it might lead to OCP bus error in
that case.
Add a new field in the sysconfig structure to specify a delay in usecs
needed after doing a softreset.
In the case of the ISS and FDIF modules, the L3 OCP port will be
disconnected upon a SW reset. That issue was confirmed with HW simulation
and an errata should be available soon. The HW recommendation to avoid
that is to wait for 100 OCP clk cycles, before accessing the IP.
Considering the worse case (OPP50), the L3 bus will run at 100 MHz,
so a 1 usec delay is needed. Add an x2 margin to be safe.
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Fernando Guzman Lugo <fernando.lugo@ti.com>
[paul@pwsan.com: dropped FDIF change for now since the hwmod data is not
yet upstream; the FDIF change will need to be added later once the FDIF
data is merged]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/omap_hwmod.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 8070145ccb98..3f26db4ee8e6 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields { * @rev_offs: IP block revision register offset (from module base addr) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) + * @srst_udelay: Delay needed after doing a softreset in usecs * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported * @clockact: the default value of the module CLOCKACTIVITY bits @@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig { u16 sysc_offs; u16 syss_offs; u16 sysc_flags; + struct omap_hwmod_sysc_fields *sysc_fields; + u8 srst_udelay; u8 idlemodes; u8 clockact; - struct omap_hwmod_sysc_fields *sysc_fields; }; /** |