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| author |   Jon Hunter <jon-hunter@ti.com> | 2012-09-28 16:09:03 -0500 |
|---|---|---|
| committer | Jon Hunter <jon-hunter@ti.com> | 2012-11-12 16:23:53 -0600 |
| commit | d3004bb43de180c2f6e965716a3abe9b43c8b861 (patch) | |
| tree | 23e3a19d361a146b13f3b7a54153b20a063ad5ea /arch/arm/plat-omap | |
| parent | ARM: OMAP: Fix dmtimer reset for timer1 (diff) | |
| download | linux-dev-d3004bb43de180c2f6e965716a3abe9b43c8b861.tar.xz linux-dev-d3004bb43de180c2f6e965716a3abe9b43c8b861.zip | |
ARM: OMAP: Don't restore of DMTIMER TISTAT register
The timer TISTAT register is a read-only register and therefore restoring the
context is not needed. Furthermore, the context of TISTAT is never saved
anywhere in the current code. The TISTAT register is read-only for all OMAP
devices from OMAP1 to OMAP4. OMAP5 timers no longer have this register.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/plat-omap')
| -rw-r--r-- | arch/arm/plat-omap/dmtimer.c | 3 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/plat/dmtimer.h | 1 |
2 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index d4f95410539f..320d10381715 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -83,9 +83,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, static void omap_timer_restore_context(struct omap_dm_timer *timer) { - if (timer->revision == 1) - __raw_writel(timer->context.tistat, timer->sys_stat); - __raw_writel(timer->context.tisr, timer->irq_stat); omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer); diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index ac16f1e9d0e0..2f9fd1d27aef 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -84,7 +84,6 @@ struct omap_dm_timer; struct timer_regs { u32 tidr; - u32 tistat; u32 tisr; u32 tier; u32 twer; |