path: root/arch/arm64/Kconfig
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authorMarc Zyngier <marc.zyngier@arm.com>2019-09-13 10:57:50 +0100
committerWill Deacon <will@kernel.org>2019-10-08 12:25:25 +0100
commit603afdc9438ac546181e843f807253d75d3dbc45 (patch)
tree3b6e284befb8384f0babee6d8afff2f6da9cb191 /arch/arm64/Kconfig
parentarm64: Avoid Cavium TX2 erratum 219 when switching TTBR (diff)
arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected
Allow the user to select the workaround for TX2-219, and update the silicon-errata.rst file to reflect this. Cc: <stable@vger.kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/Kconfig')
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 41a9b4257b72..7d36fd95ae5a 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -617,6 +617,23 @@ config CAVIUM_ERRATUM_30115
If unsure, say Y.
+config CAVIUM_TX2_ERRATUM_219
+ bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
+ default y
+ help
+ On Cavium ThunderX2, a load, store or prefetch instruction between a
+ TTBR update and the corresponding context synchronizing operation can
+ cause a spurious Data Abort to be delivered to any hardware thread in
+ the CPU core.
+ Work around the issue by avoiding the problematic code sequence and
+ trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
+ trap handler performs the corresponding register access, skips the
+ instruction and ensures context synchronization by virtue of the
+ exception return.
+ If unsure, say Y.
bool "Falkor E1003: Incorrect translation due to ASID change"
default y