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| author |   Andre Przywara <andre.przywara@arm.com> | 2017-03-07 01:17:49 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-03-27 13:44:39 +0200 |
| commit | 4e36de179f27d1017e60e25e429f50ed8382f195 (patch) | |
| tree | 0444558db7ff5c7a9cb1438fb2ae4766d3fb095f /arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi | |
| parent | ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5 (diff) | |
| download | linux-dev-4e36de179f27d1017e60e25e429f50ed8382f195.tar.xz linux-dev-4e36de179f27d1017e60e25e429f50ed8382f195.zip | |
arm64: allwinner: h5: add Allwinner H5 .dtsi
The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses
Cortex-A53 cores instead.
Based on the now shared base .dtsi describing the common peripherals
describe the H5 specific nodes on top of that.
That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi
refactor, commit message changed to meet new arm64 naming scheme,
drop H3 pinctrl compatible because of interrupt bank change, drop
H3 ccu compatible because of clock change, drop ccu node as it come
into h3-h5 dtsi]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi')
| l--------- | arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi new file mode 120000 index 000000000000..036f01dc2b9b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi @@ -0,0 +1 @@ +../../../../arm/boot/dts/sunxi-h3-h5.dtsi
\ No newline at end of file |