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| author |   Carlo Caione <ccaione@baylibre.com> | 2018-12-05 15:52:07 +0000 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2018-12-07 13:46:20 -0800 |
| commit | de7c2fa5fc9f74a2777b3bc6397a227be755f203 (patch) | |
| tree | 2d54c716fbeda47672da6f007f6b89c8a8b7b2da /arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | |
| parent | arm64: dts: meson: add clock controller clock inputs (diff) | |
| download | linux-dev-de7c2fa5fc9f74a2777b3bc6397a227be755f203.tar.xz linux-dev-de7c2fa5fc9f74a2777b3bc6397a227be755f203.zip | |
arm64: dts: meson-axg: s400: Enable PHY interrupt
Now that the GPIO controller has been enabled also on AXG we can hook up
the GPIO interrupt for the PHY.
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-axg-s400.dts')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 7759fda3ddfd..824eba98db2c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -357,6 +357,8 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + interrupt-parent = <&gpio_intc>; + interrupts = <98 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; }; |