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| author |   Arnd Bergmann <arnd@arndb.de> | 2017-10-19 23:50:15 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2017-10-20 00:38:06 +0200 |
| commit | 6260304f1a1299e595648ddbab7b60c733413a7c (patch) | |
| tree | 3ea916b34e2e554c4e375799098bc930644ea81c /arch/arm64/boot/dts/arm/foundation-v8.dtsi | |
| parent | Merge tag 'aspeed-4.15-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into next/soc (diff) | |
| parent | arm64: dts: foundation-v8: Enable PSCI mode (diff) | |
| download | linux-dev-6260304f1a1299e595648ddbab7b60c733413a7c.tar.xz linux-dev-6260304f1a1299e595648ddbab7b60c733413a7c.zip | |
Merge tag 'juno-updates-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/soc
Pull "ARMv8 Vexpress/Juno DT update for v4.15" from Sudeep Holla:
Just single update to enable PSCI support on Foundation models
* tag 'juno-updates-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: foundation-v8: Enable PSCI mode
Diffstat (limited to 'arch/arm64/boot/dts/arm/foundation-v8.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/arm/foundation-v8.dtsi | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 21a7a575f02c..78a99b58e88a 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -28,36 +28,28 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; next-level-cache = <&L2_0>; }; |