aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/arm
diff options
context:
space:
mode:
authorKevin Hilman <khilman@linaro.org>2015-06-11 14:37:45 -0700
committerKevin Hilman <khilman@linaro.org>2015-06-11 14:37:45 -0700
commitecdf94da6f91310d08081e05db78a6c997b44e4b (patch)
tree0528ddc7e2b34046b3bd98dedf89ca7fee40c1ae /arch/arm64/boot/dts/arm
parentMerge tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt (diff)
parentLinux 4.1-rc6 (diff)
downloadlinux-dev-ecdf94da6f91310d08081e05db78a6c997b44e4b.tar.xz
linux-dev-ecdf94da6f91310d08081e05db78a6c997b44e4b.zip
Merge tag 'v4.1-rc6' into next/dt
Linux 4.1-rc6 Conflicts: arch/arm/boot/dts/zynq-7000.dtsi Resolution summary: Mainline had an earlier version of the commit, resolve in favor of the newer patch in next/dt branch.
Diffstat (limited to 'arch/arm64/boot/dts/arm')
-rw-r--r--arch/arm64/boot/dts/arm/juno-motherboard.dtsi31
1 files changed, 27 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
index caf6a842f870..fde0cfad09de 100644
--- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
@@ -21,6 +21,20 @@
clock-output-names = "juno_mb:clk25mhz";
};
+ v2m_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "juno_mb:refclk1mhz";
+ };
+
+ v2m_refclk32khz: refclk32khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "juno_mb:refclk32khz";
+ };
+
motherboard {
compatible = "arm,vexpress,v2p-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
@@ -115,6 +129,15 @@
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
+ v2m_sysctl: sysctl@020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+ };
+
mmci@050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
@@ -155,16 +178,16 @@
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x10000>;
interrupts = <9>;
- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
- clock-names = "timclken1", "apb_pclk";
+ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x10000>;
interrupts = <9>;
- clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
- clock-names = "timclken1", "apb_pclk";
+ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
+ clock-names = "timclken1", "timclken2", "apb_pclk";
};
rtc@170000 {