diff options
| author |   Michael Walle <michael@walle.cc> | 2021-04-08 13:02:18 +0200 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2021-05-22 20:29:59 +0800 |
| commit | dabea675faf16e8682aa478ff3ce65dd775620bc (patch) | |
| tree | 595c21ca2cde4108ab2c25e16aab9139620627b1 /arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | |
| parent | ARM: dts: imx6q-dhcom: Add PU,VDD1P1,VDD2P5 regulators (diff) | |
| download | linux-dev-dabea675faf16e8682aa478ff3ce65dd775620bc.tar.xz linux-dev-dabea675faf16e8682aa478ff3ce65dd775620bc.zip | |
arm64: dts: ls1028a: fix memory node
While enabling EDAC support for the LS1028A it was discovered that the
memory node has a wrong endianness setting as well as a wrong interrupt
assignment. Fix both.
This was tested on a sl28 board. To force ECC errors, you can use the
error injection supported by the controller in hardware (with
CONFIG_EDAC_DEBUG enabled):
# enable error injection
$ echo 0x100 > /sys/devices/system/edac/mc/mc0/inject_ctrl
# flip lowest bit of the data
$ echo 0x1 > /sys/devices/system/edac/mc/mc0/inject_data_lo
Fixes: 8897f3255c9c ("arm64: dts: Add support for NXP LS1028A SoC")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index eca06a0c3cf8..a30249ebffa8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -197,8 +197,8 @@ ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - big-endian; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + little-endian; }; dcfg: syscon@1e00000 { |