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authorAbel Vesa <abel.vesa@nxp.com>2019-02-28 21:42:44 +0000
committerShawn Guo <shawnguo@kernel.org>2019-03-19 16:44:50 +0800
commitb810641a34702a747cb47e2cc1ecaa20f374868e (patch)
treefbcc5ed664b6a16e62ae3bbe591b07ec473e880a /arch/arm64/boot/dts/freescale
parentarm64: dts: ls1028a: Add Audio DT nodes (diff)
downloadlinux-dev-b810641a34702a747cb47e2cc1ecaa20f374868e.tar.xz
linux-dev-b810641a34702a747cb47e2cc1ecaa20f374868e.zip
arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores
The clocks and their latencies will be used by cpufreq-dt. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a1cc183a301..07f7dfff6b91 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -87,6 +87,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
@@ -95,6 +97,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
@@ -103,6 +107,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
@@ -111,6 +117,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};