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| author |   Rui Salvaterra <rsalvaterra@gmail.com> | 2022-04-28 23:57:55 +0100 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2022-05-13 13:27:40 +0200 |
| commit | 80dd27b6c68c7189b865b4b966aa12c77d1adc1e (patch) | |
| tree | 3175beeec61025243441612e4ce79a86c952b567 /arch/arm64/boot/dts/mediatek/mt7622.dtsi | |
| parent | arm64: dts: mt7622: specify the number of DMA requests (diff) | |
| download | linux-dev-80dd27b6c68c7189b865b4b966aa12c77d1adc1e.tar.xz linux-dev-80dd27b6c68c7189b865b4b966aa12c77d1adc1e.zip | |
arm64: dts: mt7622: specify the L2 cache topology
On an MT7622 system, the kernel complains of not being able to detect the cache
hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
order to fix this.
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Link: https://lore.kernel.org/r/20220428225755.785153-1-rsalvaterra@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt7622.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index da1f88d06dcc..5551f004945b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -80,6 +80,7 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -94,6 +95,12 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; }; |