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| author |   Allen-KH Cheng <allen-kh.cheng@mediatek.com> | 2022-03-18 22:45:13 +0800 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2022-04-04 14:09:36 +0200 |
| commit | 261691b40128e6b76bb94d562457d8a5236cc7fa (patch) | |
| tree | 6034d619342540a3245e530424e375b41bdc19f0 /arch/arm64/boot/dts/mediatek | |
| parent | arm64: dts: mediatek: Format mediatek,larbs as an array of phandles (diff) | |
| download | linux-dev-261691b40128e6b76bb94d562457d8a5236cc7fa.tar.xz linux-dev-261691b40128e6b76bb94d562457d8a5236cc7fa.zip | |
arm64: dts: mt8192: Add pwrap node
Add pwrap node for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220318144534.17996-2-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 411feb294613..76428599444e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -523,6 +523,18 @@ clock-names = "clk13m"; }; + pwrap: pwrap@10026000 { + compatible = "mediatek,mt6873-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; |