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| author |   Koro Chen <koro.chen@mediatek.com> | 2015-07-09 11:32:05 +0800 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2015-07-17 23:54:19 +0200 |
| commit | c02e0e86d3043e63236d7cd2e9e4259f12ac6991 (patch) | |
| tree | bea97685734065474d0e004442677469b075e2dc /arch/arm64/boot/dts/mediatek | |
| parent | arm64: dts: mt8173-evb: Add PMIC support (diff) | |
| download | linux-dev-c02e0e86d3043e63236d7cd2e9e4259f12ac6991.tar.xz linux-dev-c02e0e86d3043e63236d7cd2e9e4259f12ac6991.zip | |
arm64: dts: mt8173: Add afe device node
This adds afe (audio front end) device node to the MT8173 dtsi file.
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 359b8b6c235a..01033df1a149 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -14,6 +14,7 @@ #include <dt-bindings/clock/mt8173-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/mt8173-power.h> #include <dt-bindings/reset-controller/mt8173-resets.h> #include "mt8173-pinfunc.h" @@ -411,6 +412,37 @@ #size-cells = <0>; status = "disabled"; }; + + afe: audio-controller@11220000 { + compatible = "mediatek,mt8173-afe-pcm"; + reg = <0 0x11220000 0 0x1000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_APLL1_DIV0>, + <&topckgen CLK_TOP_APLL2_DIV0>, + <&topckgen CLK_TOP_I2S0_M_SEL>, + <&topckgen CLK_TOP_I2S1_M_SEL>, + <&topckgen CLK_TOP_I2S2_M_SEL>, + <&topckgen CLK_TOP_I2S3_M_SEL>, + <&topckgen CLK_TOP_I2S3_B_SEL>; + clock-names = "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_AUD_2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_APLL2>; + }; }; }; |