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authorNicolin Chen <nicoleotsuka@gmail.com>2019-06-17 15:16:59 -0700
committerThierry Reding <treding@nvidia.com>2019-06-20 11:17:02 +0200
commit08c7c74b0986576b0381dec58845f99f32d1542d (patch)
treea0dc200cc5a76a7428864fedcbc12d59e69972f3 /arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
parentarm64: tegra: Enable PWM on Jetson Nano (diff)
downloadlinux-dev-08c7c74b0986576b0381dec58845f99f32d1542d.tar.xz
linux-dev-08c7c74b0986576b0381dec58845f99f32d1542d.zip
arm64: tegra: Add INA3221 channel info for Jetson TX2
There are four INA3221 chips on the Jetson TX2 (p3310 + p2771). And each INA3221 chip has three input channels to monitor power. So this patch adds these 12 channels to the DT of Jetson TX2, by following the DT binding of INA3221 and official documents from https://developer.nvidia.com/embedded/downloads tegra186-p3310: https://developer.nvidia.com/embedded/dlc/jetson-tx2-series-modules-oem-product-design-guide tegra186-p2771-0000: http://developer.nvidia.com/embedded/dlc/jetson-tx1-tx2-developer-kit-carrier-board-spec-20180618 Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi40
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 4bbee83d9943..5e18acf5cfad 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -67,11 +67,51 @@
power-monitor@40 {
compatible = "ti,ina3221";
reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0x0>;
+ label = "VDD_SYS_GPU";
+ shunt-resistor-micro-ohms = <10000>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ label = "VDD_SYS_SOC";
+ shunt-resistor-micro-ohms = <10000>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ label = "VDD_3V8_WIFI";
+ shunt-resistor-micro-ohms = <10000>;
+ };
};
power-monitor@41 {
compatible = "ti,ina3221";
reg = <0x41>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0x0>;
+ label = "VDD_IN";
+ shunt-resistor-micro-ohms = <5000>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ label = "VDD_SYS_CPU";
+ shunt-resistor-micro-ohms = <10000>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ label = "VDD_5V0_DDR";
+ shunt-resistor-micro-ohms = <10000>;
+ };
};
};